Frequency references provided by oscillators are required in every clocked electronic system, including communication circuits, microprocessors, and signal processing circuits. Often, an integrated charge pump phase-locked loop (PLL) is used to generate a high frequency clock with a highly stable frequency from a somewhat lower frequency reference clock provided by an oscillator. As will be understood by those skilled in the art, to maintain loop stability within a PLL, the zero produced by the combination of the resistor R and capacitor C in the loop filter of the PLL should be as small as ⅕th or so of the open loop bandwidth, which means the capacitor C is typically very large and may occupy a considerable amount of die area, especially when the bandwidth of the PLL needs to be relatively small.
One example of a PLL that replaces the integrating function of a loop filter capacitor with a digital implementation is disclosed in U.S. Pat. No. 6,765,445 to Perrott et al., entitled “Digitally-Synthesized Loop Filter Circuit Particularly Useful for a Phase Locked Loop.” In Perrott et al., a phase error output signal of an analog phase detector is delta-sigma modulated to encode the magnitude of a phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator whose output is converted to an analog signal using a digital-to-analog converter (DAC). The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block. Another example of a PLL that utilizes an embedded analog-to-digital (ADC) converter is disclosed at FIG. 3 of an article by S. Cha et al., entitled “A Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control,” ETRI Journal, Vol. 29, No. 4, pp. 463-469, August (2007).